Summary of Changes
SDCC is a freeware, retargettable, optimizing ANSI C compiler based on gcc. It supports a number of microcontrollers, including the 14-bit core PIC microcontroller series. The SDCC project page can be found here.
I am using PIC microcontrollers for various electonics and robotics projects. Up to now, I have mostly used the PIC16F876 and PIC16F877 microcontrollers. In spring 2002, Microchip released a new series of flash PICs based on a 16-bit core. Since the new series is pin compatible with the 16F series, supports mostly the same feature set, but provides increased code space and CPU speed, I decided I should use the new series for my future projects. Unfortunately, I required new development tools, since my compiler didn't support the 18F series and it was pretty difficult to get a decent bootloader for the new chips
(I ended up writing my own bootloader - see my
PIC18F Bootloader page).
I had seen SDCC a while back, but it didn't seem to support the PIC very well. I found out to my surprise (thanks Aaron) that the latest source had good support for PIC16F series. Unfortunately, there was no support for 18F series.
I talked to Scott Dattalo who had added the 14-bit core PIC support to SDCC. He gave me directions on how I could procede with a port for the 18F series. The task seemed overwhelming at first, but fortunately, I could use a solid base (the 14-bit PIC core) as a reference point.
The 16-bit core assembler is actually more straightforward than the 14-bit core. Microchip has streamlined different areas of the microcontroller, such as memory management, stack handling, branching, multiply instructions, etc. This has made it easier to come up with the port.
I plan to use this page to keep track of progress of the PIC18F port. The first stab at the port is completed. SDCC now has basic support for the PIC18Fxx2 microcontrollers.
I can be reached at mdubuc at freeshell.org domain.
November 4, 2002: Added download section.
September 19, 2002: Added banking support.
September 18, 2002: Fixed problem with destination operand.
September 15, 2002: First PIC18F program compiled and successfully running out
In this section, I provide a list of patches that can be applied to the sdcc 2.3.2 and
gputils distributions to support the PIC18Fxx2 family. I will keep these files
around until these patches are submitted to the official SDCC distributions.
Note that during the course of my test, I was not able to get gpasm to produce
a proper hex file. I instead have used sdcc to generate the assembly file and
then MPASM to generate the .hex file. There doesn't seem to be much missing to
get .hex file out of gpasm. I just ran out of time.
Look at the sample Makefile to learn how to build programs using
PIC High Performance Microcontroller Differences
Here is a list of differences that affect the port from 16F to 18F:
- Increased flash (16k words for the PIC18Fx52)
- Increased RAM (1536 bytes for the PIC18Fx52)
- Extended configuration bits
- Enhanced stack handling (increased stack space, fast register stack)
- New instructions (RRNCF, RLNCF, MULLW, MULWF, etc.)
- Enhanced memory management (can acess the SFRs without switching banks)
- Enhanced branching support (relative addresses)
- Two levels of interrupt priority
Other differences which make the PIC18F attractive:
- Increased CPU speed
- New commands to read/write to flash
- Additional timer Timer3
PIC High Performance SDCC Port Summary of Changes
- Duplicated directory sdcc/src/pic -> sdcc/src/pic16
- Added rules for PIC18F in support/scripts/inc2ph.pl
- Modified SDCCmain.c to add support for pic16 processors:
- Modified port.h:
- Add OPT_DISABLE_PIC16 to configure.in and configure
- sdcc/src/Makefile: Add pic16/port.a to PORT_LIBS
- SDCCmain.c: Called the appropriate glue and peep rule, based on processor type.
- SDCCpeeph.c: Added debug info
- Added 18F microcontrollers to device.c
- Add new instructions to pcode.c
- Prefixed extern functions with pic16_ to avoid conflict with pic/port.a. Converted internal function to static.
- Added new parameters to POC: isAccess and isFastCall.
- In gen.c, pcode.c, pcode.h, genarith.c, ralloc.h, peeph.def, pcodepeep.c, changed INDF -> INDF0 and FSR -> FSR0.
- Moved include "*.inc" in .asm file before list of CONFIG directives.
- Changed CLRW -> CLRF WREG
- Added WREG register
- In gen.c:
Replaced RLF/RLFW with RLCF/RLCFW and RRF/RRFW with RRCF and RRCF/RRCFW.
- Added patch to avoid generation of FSR0 EQU.
- Added new status bit PIC_N_BIT, PIC_OV_BIT in pcode.h.
- Handling of access RAM and fast call operands:
In getpCode, added a condition to take into account instructions with RAM access operand
or fast call.
- Added condition to pCode2str to take into account the RAM access operand.
- Added condition in getRegFromInstruction.
- In gen.c: in genFunction, changed "GOTO END_OF_INTERRUPT+1" to "BRA END_OF_INTERRUPT+2".
- SDCCpeeph.c: select appropriate peepRules2pCode depending on processor type. Add a few
behavior code specific to PIC16 for peep handling (peepHole, initPeepHole) and in
- In ralloc.c. In aliasEQUs, do not generate EQUs for SFRs (otherwise, there is a conflict
with FSR0 bit definition).
- Define SFR as Access Bank cblock in device.c/pic16_dump_cblock
- Support new addressing scheme:
- Use MOVLB to set BSR when bank changes.
- Changed insertBankSwitch
- Changed FixRegisterBank and FixRegisterBankingInFlow
- Changed isBankInstruction
- Changed BanksUsedFlow2
- In pcode.h, removed old status bit PIC_RP0_BIT, PIC_RP1_BIT.
- Changed pic16_isREGinBank and pic16_REGallBanks
- Remove PCC_REG_BANK0, PCC_REG_BANK1, PCC_REG_BANK2, PCC_REG_BANK3
- Added isACCESS_BANK macro. Do not switch bank if register is from access bank.
- Conditionally compile mnem2key, SAFE_vsnprintf in pic16/pcode.c
PIC High Performance SDCC Port To Do List
- Create section that shows code samples of how to interface with different devices
- Fix problem with invoking function with pointer argument
- Add support for all arithmetic operations on 16-bit integers (bit shifting, etc.)
- Add support for modulo operation
- Add support for low/high priority interrupt.
- Use MULxx operations instead of genMult8X8_8
- Find where it is specified that code size for PIC18F is 16K, etc.
- Use stack feature (32 levels, no need to save/restore registers).
- Should we add PCC_LITERAL in pcc_str (pic directory)?
- Problem with RD16. Used in two places.
- Should we remove TRIS instruction (not used anywhere)?
- Use a PO for relative addresses?
- Make sure there is no additional instructions (for banking) added before RETFIE after END_OF_INTERRUPT.
can be replace with:
if source and destination registers are in the same bank.
- The default for access RAM bit is 1. Make sure that all instructions on SFRs are done with the access RAM bit set to 0 (think MPASM takes care of this).
- Do we have to add RAM access bit to cvt_altpat_mnem2, cvt_altpat_mnem2a, cvt_alpat_mnem3, etc.?
- In pCode2str, there is an if and else if with same condition.
- In ralloc.h: Is IDX_INTCON, etc. needed?
- Instruction specification:
- ADDWF does not have PCC_DC in the outCond, but ADDLW does. Why?
- All branch instructions: should we use analyseGOTO or specific analyze per instruction?
- BCF/BSF: Why dest true?
- Should we set PCC_EXAMINE_PCOP for other instructions?
- ANDFW didn't have dest set to 1. Is this normal?
- For BC, should we put PCC_C as inCond?
- How to express expressions on two words such as CALL?
- Why not put PCC_REGISTER as inCond of CLRF?
- Why INCF does not have C, DC, Z, etc. for outCond?
- Find a way to specify there are two registers.
- Why is there a MOVWF? Same as MOVF?
- Why no PCC_W in outCond of MOVF?
- Add C, DC to SUBWF/SUBFW?
- Why DC and C in XORLW outCond?
- How to specify FSRx in LFSR?
- Why is POC_BCF towards end of POC_BSF. What should we use for POC_BTG?
Last updated: July 12, 2005